Date portal Nürnberg

This track addresses design automation, design tools and hardware architectures for electronic and embedded systems.

The emphasis is on methods, algorithms and tools related to the use of computers in designing complete systems.

This track is devoted to the presentation and discussion of design experiences with a high degree of industrial relevance, as well as applications of specific design and test methodologies.

Reconfigurable computing platforms and architectures; heterogeneous platforms (FPGA/GPU/CPU); reconfigurable processors; reconfigurable computing for high performance and data centers; statically and dynamically reconfigurable and reprogrammable systems and components; FPGA architectures and FPGA circuit design; design methods and tools for reconfigurable computing and communication systems.Modeling, circuit design and design automation flows for future computing including: non-CMOS logic based on emerging devices (e.g., carbon nanotube or graphene based FETs, TFETs, NWFETs, single electron transistors, NEMS etc.); alternative interconnect technologies (e.g., optical, RF, 3D, carbon nanotubes, graphene nanoribbons, spintronics, etc.); monolithic 3D integration (TSV modeling and design space exploration). Be 2 partnersuche Modeling, circuit design and design automation flows for future data storage including: non-CMOS memory (e.g., MRAM, STT-RAM, Fe RAM, PCRAM, RRAM, Ox RAM, quantum dots etc.); advances in flash memory technology; memory-centric architectures (e.g., logic-in-memory, associative memories, non-volatile cache etc.); memory management techniques for emerging memories.In topic A8, there is the opportunity to submit short, 2-page papers that relate to industrial research and practice.Track Chair: Ian O'Connor, Ecole Centrale de Lyon, FR, Contact Ian O' Connor Topics Application design experiences in industrial or academic projects with high industrial relevance or high environmental impact, targeting high performance or large-scale computing systems with a focus on energy efficiency.

Date portal Nürnberg

This includes analogue and mixed-signal integrated circuits, micro-electromechanical systems, high voltage structures, integrated sensors and transducers, RF architectures, in-vehicle networks, systems for electric vehicles, networks of systems (including car-to-car and car-to-infrastructure networks), and innovative concepts for power distribution, energy storage, and grid monitoring.Finally, topics of interest are also hardware solutions for run-time system management, including self-diagnostics and repair, energy generation, energy saving, novel energy harvesting, battery management, renewable energy subsystems, and optimization of system energy efficiency.The track’s focus includes significant improvements on existing design methods and tools as well as forward-looking approaches to model and design future system architectures, design flows, and environments.Track Chair: Ayse Kivilcim Coskun, Boston University, US, Contact Ayse Kivilcim Coskun Topics Modeling and specification methodologies for complex HW-SW systems; (formal) models of computation and their (static) analysis; modeling and analysis of functional and non-functional system properties; concurrency models; multi-domain/multi-criteria specifications and models; application and workload models; requirements engineering; system-level modeling and simulation of multi- and many-core So Cs; Transaction Level Modeling (TLM) and model refinement; modeling of system adaptivity; system modeling and specification languages; model-driven engineering; meta-modeling; executable specifications; specification driven design and validation flows.Track Chair: Giorgio Di Natale, LIRMM, FR, Contact Giorgio Di Natale Topics Identification, characterization and modeling of defects, faults and degradation mechanisms in conventional, advanced and emerging technologies (Fin FET, FDSOI, TSV, Memristor, MTJ, CNT…); defect-based fault analysis; reliability analysis and modeling at device, circuit and component level; process yield modeling and enhancement; design-for-manufacturability and design-for-yield; noise and uncertainty modeling at circuit and component level; modeling and mitigation of physical sources of errors such as process, voltage, temperature and aging variations at circuit and component level; Algorithms for test pattern generation (TPG); TPG for delay and small-delay faults; TPG for low power; Algorithms for test compression and compaction; ATPGs; Fault simulation; Diagnosis; Power Issues in Testing; Test generation for: Microprocessors, Memories, FPGAs and regular structures; Algorithms for board and system test; Volume diagnosis and yield analysis Architectures and solutions for design for test, diagnosis, debug, post silicon validation; BIST and embedded test; Power-On Self-Test; Test architectures and infrastructures for memories, FPGAs, 2.5D, 3D, Si P, No C, Microprocessors; Test Infrastructures for Secure Devices; Test principles and methods for design-for-trust; ATE architectures; Test Standards (JTAG, IJTAG, 1500, P1838)Fault models: Permanent, Transient and Soft Errors; Dependability Evaluation; Space-, Time- and Information-redundancy based dependability solutions; Highly-Available Systems; Reliable, Secure and Fail-Safe System Design; HW/SW solutions for on-line fault detection, tolerance, recovery and aging mitigation; Countermeasures Against Fault Attacks.

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It is devoted to modeling, analysis, design and deployment of embedded software.Formal verification and specification techniques (including equivalence checking, model checking, symbolic simulation, theorem proving, abstraction and decomposition techniques); technologies supporting formal verification; semi-formal verification techniques; formal verification of IPs, So Cs, and cores; integration of verification into design flows; challenges of multi-cores, both as verification targets and as verification host platforms.Layout and topology generation; architecture, system and circuit synthesis and optimization; formal and symbolic techniques; hardware description languages and models of computation; innovative circuit topologies and architectures; MEMS; self-healing and self-calibration; test generation; fault modeling and simulation; built-in self-test; design-for-test; fault diagnosis; defect characterization and failure analysis; on-line test and fault tolerance; design-for-manufacturability and design-for-yield; test metrics and economics.Application design experiences for communication, multimedia and consumer systems such as smartphones, smart-books/tablets including digital integrated circuit design of flexible baseband processing systems, Intellectual Properties for wireless communication, design challenges for software-defined/cognitive radio systems; embedded systems design in the field of audio, video and computer vision domains; Application Specific Processors (ASP), Digital Signal Processors (DSP), Multi-Processor Systems on Chip (MPSo C) and Network on Chip (No C) designs for these domains.Design experiences for automotive systems, smart energy systems, energy scavenging and harvesting for embedded systems, and related applications.

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